Techniques to lower the operating voltages of single semiconductor memory devices (or chips) or the operating voltages of the internal memory modules of chips have been proposed to reduce the power consumption of semiconductor memory devices.
However, lowered operating voltages present difficulties with interfacing between semiconductor memory devices and external systems as well as difficulties due to lowered internal voltages. To solve the interface problem with external systems requires a specific regulator or interface circuit to overcome the operating voltage difference between memory devices and external systems. The additional interface circuitry increases chip area and power consumption.
Difficulties due to lowered internal voltages arise in chip manufacturing and design. In other words, lowered threshold voltages resulting from the operation of an internal device at a lower voltage causes leakage currents, and lowers the reliability due to the breakdown voltage decrease and reduces stability due to noise susceptibility.
The research for more economical power consumption of memory devices has progressed by reducing the power consumption of the memory itself, instead of lowering the operating voltage, because of the difficulties described above. The methods to reduce power consumption in memory devices until now have been to improve the amplifier structure of the memory output terminals, using a low-voltage swing bus and multi-divided modules, and to reduce the memory area. Additionally, a method of moving the output terminals of the memory data to both sides to reduce the bit line capacitance and improve the operating speed was also proposed. Various techniques to reduce the power consumed in precharging the bit lines have been proposed.
FIG. 1 is a circuit diagram of a semiconductor memory device according to the prior art, as an example an SRAM (Static Random Access Memory), which includes a memory cell array, a column selection circuit 50, a bit line precharge circuit 60, a write driver circuit 40 and a sense amplifier 30.
The memory cell array is constructed of memory cells 10, in which the memory cells 10 are arranged in rows and columns. The memory cells 10 are connected with three signal lines, a bit line BL, a complementary bit line BLb and a word line SWL.
The desired word line SWL is selected by a row selection circuit (not shown) operating in response to a row address request.
The column selection circuit 50 is constructed of CMOS (Complementary Metal Oxide Semiconductor) circuits 52 and 54 that respond to a column enable signal PYB and an inversion signal of the column enable signal PYB.
The column selection circuit 50 selects a pair of bit lines BL and BLb connected to the memory cells 10 in response to the column enable signal PYB applied through a column decoder 70 operated from an internal power source voltage Vcc, by using a column address request, and connects them with data lines DL and DLb. The selected bit line pair BL and BLb is connected with a sense amplifier 30 and a write driver circuit 40 through the data line pair DL and DLb corresponding to the selected bit line pair BL and BLb.
The bit line precharge circuit 60 precharges the bit line pair BL and BLb connected to the memory cells 10.
In the bit line precharge circuit 60, three PMOS transistors 62, 64 and 66 are connected with the bit line pair BL and BLb. The PMOS transistors 64 and 66 have current paths individually formed between bit lines BL and BLb corresponding to the internal power source voltage Vcc. The PMOS transistor 62 has a current path formed between the bit line pair BL and BLb. The PMOS transistors 62, 64 and 66 are commonly controlled by the bit line precharge signal from the inversion signal of the column enable signal PYB. That is, the PMOS transistors 62, 64 and 66 are switched simultaneously by the bit line precharge voltage level.
The write driver circuit 40 is constructed of NAND gates 41 and 42, PMOS transistors 43 and 46, and NMOS transistors 44, 45, 47 and 48, and drives data DIN on data lines DL and DLb in response to a data write signal PWD in a write operation.
The sense amplifier 30 senses and amplifies data of the memory cells in response to a sense amplifier enable signal PSA in a read operation.
Additionally, the semiconductor memory device according to the prior art includes a data line precharge circuit 80, which is constructed of PMOS transistors 82, 84 and 86 to precharge the data lines. The PMOS transistors 82 and 86 have current paths individually formed between data lines DL and DLb corresponding to the internal power source voltage Vcc. The PMOS transistor 84 has a current path formed between the data line pair DL and DLb.
FIG. 2 is a timing diagram for the operations of FIG. 1, wherein a write operation for data in a semiconductor memory device according to the prior art will be described as follows.
Data DIN is transferred to data lines DL and DLb in response to the data write signal PWD. Then, full voltage swing data is transferred to bit lines BL and BLb through a CMOS transistor of the column selection circuit 50 that responds to the column enable signal PYB. When the word line SWL is enabled, one pair of data is written in a selected memory cell 10 through selected bit lines BL and BLb. The voltage level of the bit lines BL and BLb is swung between the internal power source voltage Vcc and a standard ground voltage Vss.
In such a conventional semiconductor memory device, one pair of bit lines is connected with many cells, e.g., 2K˜8K, and data lines are also connected with column selection circuits of the same number as the number of columns. Thus, the loading capacitance in these circuits becomes a factor by consuming large amounts of power in a semiconductor memory device. In particular, in a write operation, the precharge operation having a full voltage swing between the internal power source voltage Vcc and the standard ground voltage Vss of the data line and the bit line becomes a cause of large power consumption in the conventional semiconductor memory device. This is a serious obstacle to efficiently obtaining products having small power consumption.